Fault-avoidance C-element based low overhead and TNU-resilient latch

作者：Huang, Zhengfeng; Gong, Zhouyu; Ma, Dongxing; Wang, Xiaolei; Lu, Yingchun; Zhan, Wenfa; Liang, Huaguo; Ni, Tianming^*

来源：MICROELECTRONICS JOURNAL, 2023, 131: 105650.

DOI：10.1016/j.mejo.2022.105650

• Hardened latch design
• Low overhead
• C-element
• Triple-node-upset resilience

Single event upset (SEU) threatens the reliability of spaceborne integrated circuits (ICs). As the process of transistors continues to scale, Single-Node-Upset (SNU) and Double-Node-Upset (DNU) hardened circuits no longer meet the requirements of high reliability. A disadvantage of previous Triple-Node-Upset (TNU) hardened circuits is high overhead. Therefore, this paper proposes a fault-avoidance TNU-resilient latch (FATNU) using approximate C-elements (ACs) and new fault-avoidance C-elements (FACs). Simulation results demonstrate that FATNU achieves TNU resilience with low overhead compared with reference latches due to the use of the clock -gating technique and cross-feedback loop. In particular, compared with previous TNU-resilient latches, the FATNU latch is the best in delay, power, and area overhead. Moreover, the proposed FATNU latch is insensitive to process, voltage, and temperature (PVT) variations.