13 GHz Programmable Frequency Divider in 65 nm CMOS

作者：Kang, Jian^*; Qin, Peng; Li, Xiaoyong; Mo, Tingting

来源：IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), China,Shaanxi,Xian, 2012-10-29 To 2012-11-01.

DOI：10.1109/ICSICT.2012.6467883

• CMOS processs
• D flip-flops
• Dual modulus prescaler
• Frequency dividers
• High speed frequency divider
• Programmable frequency divider
• Voltage supply

This paper presents a CMOS high speed frequency divider which can operate at up to 13GHz. The divider core is composed of a divide by 8/9 dual modulus prescaler and a programmable digital counter. The divide by 8/9 dual modulus prescaler is realized by CML structure which operates around 6GHz. The digital counter is composed of logic gates and TSPC D flip-flops which operate at around 700MHz. The total division ratio is programmable and controlled by the input to the digital counter. The proposed frequency divider is designed and simulated in a 65 nm CMOS process and is capable of working robustly over the process, voltage supply, and temperature (P.V.T) variations.

• 单位
  上海交通大学