科研之友
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摘要
Low-dimensional materials have been proposed as alternatives to silicon-based field-effect transistor (FET) channel materials in order to overcome the scaling limitation. In the present research, gate-all-around (GAA) Sb2Se3 nanowire FETs were simulated using the ab initio quantum transport method. The gate-length (L-g, L-g = 5 nm) GAA Sb2Se3 FETs with an underlap (UL, UL = 2, 3 nm) could satisfy the on-state current (I-on) and delay time (tau) of the 2028 requirements for high performance (HP) applications of the International Technology Roadmap for Semiconductors (ITRS) 2013. It is interesting that the L-g = 3 nm GAA Sb2Se3 FETs with a UL = 3 nm can meet the I-on, power dissipation (PDP), and tau of the 2028 requirements of ITRS 2013 for HP applications. Therefore, GAA Sb2Se3 FETs can be a potential candidate scaling Moore's law downward to 3 nm.
