Compact Modeling of Process Variations in Nanosheet Complementary FET (CFET) and Circuit Performance Predictions

摘要

In this work, a semi-analytical compact model of random process fluctuations in nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work-function variation (WFV), line edge roughness (LER), and gate edge roughness (GER). Different from the conventional NS GAA FET, GER has a significantly different impact on NS GAA CFET, due to the additional p-type work-p-WF) liner for p-FET threshold voltage tuning as well as the common metal gate, and a negative correlation with p-WF thickness is introduced into GER model. The proposed model is embedded into Berkeley short-channel insulated-gate field-effect transistor model-common multi-gate (BSIM-CMG) to predict the device performance variability by HSPICE Monte Carlo (MC) simulations. Excellent agreement between stochastic TCAD and HSPICE MC simulations is demonstrated. The effect of process variations on the power-performance-area (PPA) of standard cells (SDCs) and ring oscillator (RO) circuit is predicted by the proposed model. Most of the process variations make a more than -10% to +20% change in power consumption in NOR2. WFV has the greatest impact on RO PPA, making a -10% to +12.3% change in power consumption. The proposed model provides a helpful guideline for the random variation-aware CFET circuit design and related technology process development.

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