A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF[Formula: see text]

作者：Poolakkaparambil M; Mathew J; Jabir A M; Pradhan D K

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014.

DOI：10.1109/TVLSI.2014.2341631

This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF (2m). For an m input circuit, the proposed scheme can correct m ≤ Dw ≤ 3m/2-1 multiple error combinations out of all the possible 2m-1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106 and 170 area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.