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Design Challenges of Intrachiplet and Interchiplet Interconnection

Chen, Chixiao; Yin, Jieming; Peng, Yarui; Palesi, Maurizio; Cao, Wenxu; Huang, Letian; Singh, Amit Kumar; Zhi, Haocong; Wang, Xiaohang*
Science Citation Index Expanded
电子科技大学; 复旦大学; 南京邮电大学; 浙江大学; i

摘要

This article discusses the challenges in intrachiplet and interchiplet networks, including the need for faster simulation, better architectures, and performance requirements determined by emerging applications.

关键词

Routing System recovery Standards Integrated circuit modeling Multiprocessor interconnection Logic gates Data models System analysis and design System-on-chip Chiplet inter- and intra-chiplet interconnection