Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation

摘要

As the ICs become more complex, the duration of high-cost specification tests is increasingly important, especially given the total IC expenditure. In our current work, we propose an adaptive test strategy for reducing the duration of delay testing. This method employs pattern permutation with an ML algorithm to improve the test efficiency, followed by an examination of the effect of test performance, temperature, and voltage on the recognition of path delay defects. SPICE simulations under different voltage and temperature conditions with 65-nm CMOS technology were used to validate it. According to the experimental outcomes, when compared to the random ordering method, the proposed method successfully achieves a nearly 7-fold improvement in test quality at identical testing duration or a 25% reduction in the duration at identical test quality. In addition, the method provides the tester with a thorough understanding of the test efficiency contributions.

关键词