REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip

作者：Ouyang, Yiming; Xu, Dongyu^*; Chen, Zhimou; Chen, Rongjing; Zhou, Wu; Liang, Huaguo

来源：MICROELECTRONICS JOURNAL, 2022, 129: 105600.

DOI：10.1016/j.mejo.2022.105600

• Wireless network on chip
• Power gating
• Reconfigurable
• Energy -efficient
• Wireless interface

Currently, on-chip routers consume the majority of the power budget. Moreover, the static power consumption has taken up a significant fraction of the total power consumption in the router. Especially in the light traffic state, the router idle time is notable, but fragmented owing to the impact of some burst traffic, increasing the challenge of reducing static power consumption through power gating. In this paper, a reconfigurable and energy-efficient router architecture design (REE) is proposed: bypass connections are set for routers, and deflection rules are formulated to ensure that routers maintain connectivity in the network under power gating situation, and reduce the deflection rate of packets encountering sleeping routers. Meanwhile, a reusable predictor is introduced to efficiently predict the idle time to wake up the sleeping router appropriately. In addition, the fine-grained power gating (PG) design is introduced in the wireless interface of wireless routers (WRs) to obtain the scheme REE+, which reduces the idle time of transmitter (TX) components and effectively saves the static power consumption of Wireless Interface. Experiments demonstrate that both the REE and REE + schemes in this paper have negligible impact on latency as well as throughput, while the energy savings are significant: 64.5% and 68.3% average static power savings for REE and REE + schemes, respectively, compared to No_PG, and 13.7% and 20.5% average improvement in terms of static power saving compared to Turn-on on Turn (TooT), respectively.