Gate-Controlled Memristor FPGA Model for Quantified Neural Network

作者：Zhang, Zhang; Xu, Ao; Li, Chao; Wei, Yadong; Ge, Zhiheng; Cheng, Xin^*; Liu, Gang

来源：IEEE Transactions on Circuits and Systems II: Express Briefs , 2022, 69(11): 4583-4587.

DOI：10.1109/TCSII.2022.3192616

• Gate-controlled memristor
• quantified neural network
• FPGA
• multiply-accumulate circuit
• RTL-level circuit simulation

The gate-controlled memristor has evident advantages over the traditional 2-terminal memristor in the field of the application of quantified neural networks. Since it is difficult to realize the large-scale integration, developing a flexible emulator of gate-controlled memristor is essential to explore different possible applications of neural networks. However, existing previous works of the gate-controlled memristor model lack flexibility and portability. This brief presents a novel FPGA model of gate-controlled memristor, verified on a Xilinx XQ7Z020 chip with less than 1% hardware resource utilization. And a novel approach utilizing the local linearity property of the device conductance to construct a multiply-accumulate circuit architecture has been proposed herein. Moreover, a benchmark of 4-state quantified single-layer perceptron using the proposed model has been validated with the MNIST dataset. The experimental results show that the circuit reaches the recognition accuracy of 87.6% on 10,000 images of MNIST, which differs from the PyTorch result only by 0.03%.

• 单位
  上海交通大学