A Low-Cost Triple-Node-Upset Self-Recovery Latch Design*

作者：Xu, Hui; Xia, Yu; Ma, Ruijun; Liang, Huaguo^*; Huang, Zhenfeng

来源：JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2024.

DOI：10.1142/S0218126624501792

• Triple-node-upset
• single-event-upset
• soft error
• self-recovery

As the CMOS process continues to decrease in size, the latch becomes increasingly vulnerable to the triple-node-upset (TNU), leading to a decrease in circuit reliability in harsh radiation environments. In this paper, a low-cost TNU self-recovery latch (LCTR) is proposed, which is based on one PMOS and two NMOS (1P2N) inverters and C-elements (CEs) forming a multi-level feedback loop. Due to the error interception function of these fundamental elements, the proposed latch completely realizes TNU self-recovery capability. Then the simulated tests are used for comparing the overhead of the LCTR latch and the other two typical TNU self-recoverable latches. The results reveal that the LCTR latch decreases power consumption by 56.98%, delay by 30.08%, area by 21.25% and PDP by 70.77%, respectively. Moreover, the LCTR latch is moderately sensitive to the variation of process, voltage and temperature (PVT).